EP1AGX90EF1152I6N Altera, EP1AGX90EF1152I6N Datasheet - Page 49

IC ARRIA GX FPGA 90K 1152FBGA

EP1AGX90EF1152I6N

Manufacturer Part Number
EP1AGX90EF1152I6N
Description
IC ARRIA GX FPGA 90K 1152FBGA
Manufacturer
Altera
Series
Arria GXr
Datasheet

Specifications of EP1AGX90EF1152I6N

Number Of Logic Elements/cells
90220
Number Of Labs/clbs
4511
Total Ram Bits
4477824
Number Of I /o
538
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2387

Available stocks

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Quantity
Price
Part Number:
EP1AGX90EF1152I6N
Manufacturer:
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10 000
Part Number:
EP1AGX90EF1152I6N
Manufacturer:
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0
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–38. Register Chain within a LAB
Note to
(1) The combinational or adder logic can be used to implement an unrelated, unregistered function.
Clear and Preset Logic Control
© December 2009 Altera Corporation
Figure 2–38
:
LAB-wide signals control the logic for the register ’s clear and load/preset signals. The
ALM directly supports an asynchronous clear and preset function. The register preset
is achieved through the asynchronous load of a logic high. The direct asynchronous
preset does not require a NOT gate push-back technique. Arria GX devices support
simultaneous asynchronous load/preset and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one load/preset signal.
Combinational
Combinational
Logic
Logic
(Note 1)
adder0
adder1
adder0
adder1
reg_chain_out
reg_chain_in
D
D
D
D
reg0
reg1
reg0
reg1
From Previous ALM
Within The LAB
To Next ALM
within the LAB
Q
Q
Q
Q
To general or
To general or
To general or
To general or
To general or
To general or
To general or
To general or
Arria GX Device Handbook, Volume 1
local routing
local routing
local routing
local routing
local routing
local routing
local routing
local routing
2–43

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