EP2SGX60EF1152C5N Altera, EP2SGX60EF1152C5N Datasheet - Page 23

• Manufacturer Part Number: EP2SGX60EF1152C5N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C5N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2185

Altera Corporation
October 2007
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Receiver Input Buffer
The Stratix II GX receiver input buffer supports the 1.2-V and 1.5-V
PCML I/O standard at rates up to 6.375 Gbps. The common mode voltage
of the receiver input buffer is programmable between 0.85 V and 1.2 V.
You must select the 0.85 V common mode voltage for AC- and
DC-coupled PCML links and the 1.2 V common mode voltage for
DC-coupled LVDS links.
The receiver has programmable on-chip 100-, 120-, or 150-Ω differential
termination for different protocols, as shown in
receiver’s internal termination can be disabled if external terminations
and biasing are provided. The receiver and transmitter differential
termination resistances can be set independently of each other.
Figure 2–12. Receiver Input Buffer
Programmable Termination
The programmable termination can be statically set in the Quartus II
software.
termination. The termination can be disabled if external termination is
provided.
Input
Pins
Lane deskew
Rate matcher
8B/10B decoder
Byte deserializer
Byte ordering
Receiver phase compensation FIFO buffer
Figure 2–13
Programmable
Termination
shows the setup for programmable receiver
Stratix II GX Device Handbook, Volume 1
Programmable
Equalizer
Figure
Stratix II GX Architecture
2–12. The
Differential
Buffer
Input
2–15