EP2S180F1508C3 Altera, EP2S180F1508C3 Datasheet - Page 26

• Manufacturer Part Number: EP2S180F1508C3
• Description: IC STRATIX II FPGA 180K 1508FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S180F1508C3

• Number Of Logic Elements/cells: 179400
• Number Of Labs/clbs: 8970
• Total Ram Bits: 9383040
• Number Of I /o: 1170
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1508-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 179400
• # I/os (max): 1170
• Frequency (max): 778.82MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 179400
• Ram Bits: 9383040
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1508
• Package Type: FC-FBGA
• For Use With: 544-1701 - DSP PRO KIT W/SII EP2S180N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2164

Adaptive Logic Modules
Figure 2–13. ALM in Shared Arithmetic Mode
Note to
(1)
2–18
Stratix II Device Handbook, Volume 1
Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Figure
datae0
datae1
datab
dataa
datad
datac
2–13:
Adder trees can be found in many different applications. For example, the
summation of the partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology.
An example of a three-bit add operation utilizing the shared arithmetic
mode is shown in
partial carry (C[2..0]) is obtained using the LUTs, while the result
(R[2..0]) is computed using the dedicated adders.
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
Figure
carry_out
carry_in
2–14. The partial sum (S[2..0]) and the
D
D
reg0
reg1
Q
Q
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
Altera Corporation
May 2007