XC5VLX110-1FFG676C Xilinx Inc, XC5VLX110-1FFG676C Datasheet - Page 120
![IC FPGA VIRTEX-5 110K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110-1FFG676C
Manufacturer Part Number
XC5VLX110-1FFG676C
Description
IC FPGA VIRTEX-5 110K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-1FFG676C
Total Ram Bits
4718592
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Gates
110000
Family Type
Virtex-5 LX
No. Of Speed Grades
1
No. Of I/o's
440
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1557
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Chapter 4: Block RAM
Additional Block RAM Features in Virtex-5 Devices
X-Ref Target - Figure 4-5
120
CLK
WE
Optional Output Registers
Independent Read and Write Port Width Selection
EN
Optional
Inverter
Address
DI
The optional output registers improve design performance by eliminating routing delay to
the CLB flip-flops for pipelined operation. An independent clock and clock enable input is
provided for these output registers. As a result the output data registers hold the value
independent of the input register operation.
Each block RAM port has control over data width and address depth (aspect ratio). The
true dual-port block RAM in Virtex-5 FPGAs extends this flexibility to Read and Write
where each individual port can be configured with different data bit widths. For example,
port A can have a 36-bit Read width and a 9-bit Write width, and port B can have a 18-bit
Read width and a 36-bit Write width. See
If the Read port width differs from the Write port width, and is configured in
WRITE_FIRST mode, then DO shows valid new data for all the enabled write bytes. The
DO port outputs the original data stored in memory for all not enabled bytes.
Independent Read and Write port width selection increases the efficiency of implementing
a content addressable memory (CAM) in block RAM. This option is available for all
Virtex-5 FPGA true dual-port RAM port sizes and modes.
Figure 4-5: Block RAM Logic Diagram (One Port Shown)
Register
Strobe
Write
(common to
both ports)
Memory
Array
www.xilinx.com
Read
Strobe
Control Engine
D
Latches
Block RAM Attributes, page
Figure 4-5
Latch
Enable
Q
Configurable Options
shows the optional output register.
D
Register
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Q
128.
UG190_4_06_040606
DO
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