XC5VLX110-1FFG676C Xilinx Inc, XC5VLX110-1FFG676C Datasheet - Page 321
![IC FPGA VIRTEX-5 110K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110-1FFG676C
Manufacturer Part Number
XC5VLX110-1FFG676C
Description
IC FPGA VIRTEX-5 110K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-1FFG676C
Total Ram Bits
4718592
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Gates
110000
Family Type
Virtex-5 LX
No. Of Speed Grades
1
No. Of I/o's
440
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1557
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X-Ref Target - Figure 7-4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CE
Q1
Q2
C
D
Input DDR Primitive (IDDR)
D0A D1A D2A
Figure 7-4: Input DDR Timing in SAME_EDGE_PIPELINED Mode
Figure 7-5
signals.
primitive.
X-Ref Target - Figure 7-5
Table 7-3: IDDR Port Signals
Q1 and Q2
C
CE
D
R
S
Name
Port
Table 7-4
D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A
shows the block diagram of the IDDR primitive.
D1A
D0A
Data outputs
Clock input port
Clock enable port
Data input (DDR) IDDR register input from IOB.
Reset
Set
describes the various attributes available and default values for the IDDR
Function
Figure 7-5: IDDR Primitive Block Diagram
www.xilinx.com
D2A
D3A
CE
D
C
The C pin represents the clock input pin.
The enable pin affects the loading of data into the DDR
IDDR register outputs.
flip-flop. When Low, clock transitions are ignored and new
data is not loaded into the DDR flip-flop. CE must be High
to load new data into the DDR flip-flop.
Synchronous/Asynchronous reset pin. Reset is asserted
High.
Synchronous/Asynchronous set pin. Set is asserted High.
R
S
D4A
D5A
IDDR
ug190_7_05_062207
D6A
D7A
Description
Q1
Q2
Table 7-3
D8A
D9A
ug190_7_04_041206
lists the IDDR port
ILOGIC Resources
D10A
D11A
321
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