EP2C5Q208I8N Altera, EP2C5Q208I8N Datasheet - Page 137
![IC CYCLONE II FPGA 5K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EP2C5Q208I8N
Manufacturer Part Number
EP2C5Q208I8N
Description
IC CYCLONE II FPGA 5K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C5Q208I8N
Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
142
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-MQFP, 208-PQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
4608
# I/os (max)
142
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
4608
Ram Bits
119808
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2135
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C5Q208I8N
Manufacturer:
Altera
Quantity:
1 948
Company:
Part Number:
EP2C5Q208I8N
Manufacturer:
ALTERA41
Quantity:
228
Part Number:
EP2C5Q208I8N
Manufacturer:
ALTERA
Quantity:
20 000
Altera Corporation
February 2008
LVTTL
2.5V
1.8V
1.5V
LVCMOS
SSTL_2_CLASS_I
SSTL_2_CLASS_II
SSTL_18_CLASS_I
SSTL_18_CLASS_II
1.5V_HSTL_CLASS_I
1.5V_HSTL_CLASS_II
1.8V_HSTL_CLASS_I
1.8V_HSTL_CLASS_II
PCI
PCI-X
DIFFERENTIAL_SSTL_2_
CLASS_I
DIFFERENTIAL_SSTL_2_
CLASS_II
Table 5–44. Maximum Input Clock Toggle Rate on Cyclone II Devices (Part 1 of 2)
I/O Standard
For example, the output toggle rate at 0 pF (default) load for SSTL-18
Class II 18mA I/O standard is 270 MHz on a
The derating factor is 29 ps/pF. For a 10pF load, the toggle rate is
calculated as:
Tables 5–44
devices.
= 1000 / (1000/toggle rate at default load + derating factor * load
value in pF/1000)
1000 / (1000/270 + 29 × 10/1000) = 250 (MHz)
Speed
Grade
450
450
450
300
450
500
500
500
500
500
500
500
500
500
500
–6
—
—
Column I/O Pins
Maximum Input Clock Toggle Rate on Cyclone II Devices (MHz)
through
Speed
Grade
405
405
405
270
405
500
500
500
500
500
500
500
500
500
500
–7
—
—
5–46
Speed
Grade
360
360
360
240
360
500
500
500
500
500
500
500
500
500
500
–8
—
—
show the I/O toggle rates for Cyclone II
DC Characteristics and Timing Specifications
Speed
Grade
500
500
500
500
450
450
450
300
450
500
500
500
500
350
350
500
500
–6
Row I/O Pins
Cyclone II Device Handbook, Volume 1
Speed
Grade
405
405
405
270
405
500
500
500
500
500
500
500
500
315
315
500
500
–7
Speed
Grade
–
500
500
500
500
360
360
360
240
360
500
500
500
500
280
280
500
500
–8
6 device column I/O pin.
Speed
Grade
420
450
450
300
420
500
500
500
500
500
500
500
500
350
350
500
500
–6
Dedicated Clock
Inputs
Speed
Grade
380
405
405
270
380
500
500
500
500
500
500
500
500
315
315
500
500
–7
Speed
Grade
340
360
360
240
340
500
500
500
500
500
500
500
500
280
280
500
500
5–47
–8