EP2C5Q208I8N Altera, EP2C5Q208I8N Datasheet - Page 39
![IC CYCLONE II FPGA 5K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EP2C5Q208I8N
Manufacturer Part Number
EP2C5Q208I8N
Description
IC CYCLONE II FPGA 5K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C5Q208I8N
Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
142
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-MQFP, 208-PQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
4608
# I/os (max)
142
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
4608
Ram Bits
119808
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2135
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C5Q208I8N
Manufacturer:
Altera
Quantity:
1 948
Company:
Part Number:
EP2C5Q208I8N
Manufacturer:
ALTERA41
Quantity:
228
Part Number:
EP2C5Q208I8N
Manufacturer:
ALTERA
Quantity:
20 000
Figure 2–16. Cyclone II PLL
Notes to
(1)
(2)
Embedded
Memory
Altera Corporation
February 2007
CLK0 (1)
CLK2 (1)
CLK1
CLK3
This input can be single-ended or differential. If you are using a differential I/O standard, then two CLK pins are
used. LVDS input is supported via the secondary function of the dedicated CLK pins. For example, the CLK0 pin’s
secondary function is LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. If a differential I/O
standard is assigned to the PLL clock input pin, the corresponding CLK(n) pin is also completely used. The
Figure 2–16
This counter output is shared between a dedicated external clock output I/O and the global clock network.
Figure
2–16:
shows the possible clock input connections (CLK0/CLK1) to PLL1.
inclk0
inclk1
f
Manual Clock
Select Signal
Switchover
f
IN
Figure 2–16
For more information on Cyclone II PLLs, see the PLLs in the Cyclone II
Devices chapter in Volume 1 of the Cyclone II Device Handbook.
The Cyclone II embedded memory consists of columns of M4K memory
blocks. The M4K memory blocks include input registers that synchronize
writes and output registers to pipeline designs and improve system
performance. The output registers can be bypassed, but input registers
cannot.
÷n
f
Input Clock
REF
f
Reference
FB
Note (1)
= f
IN
/n
PFD
shows a block diagram of the Cyclone II PLL.
down
up
Charge
Pump
Lock Detect
& Filter
÷m
Loop
Filter
Cyclone II Device Handbook, Volume 1
VCO
f
VCO
(3)
÷k
VCO Phase Selection
Selectable at Each
PLL Output Port
8
8
8
Cyclone II Architecture
Post-Scale
Counters
÷c0
÷c1
÷c2
(2)
Global
Clock
Global
Clock
Global
Clock
PLL<#>_OUT
To I/O or
general routing
2–27