EPF6024AQC240-2 Altera, EPF6024AQC240-2 Datasheet - Page 17
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EPF6024AQC240-2
Manufacturer Part Number
EPF6024AQC240-2
Description
IC FLEX 6000 FPGA 24K 240-PQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet
1.EPF6010ATC100-3N.pdf
(52 pages)
Specifications of EPF6024AQC240-2
Number Of Logic Elements/cells
1960
Number Of Labs/clbs
196
Number Of I /o
199
Number Of Gates
24000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-1286
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF6024AQC240-2
Manufacturer:
ALTERA
Quantity:
1 150
Part Number:
EPF6024AQC240-2
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 8. LE Clear & Preset Modes
Asynchronous Clear
Asynchronous Preset
labctrl1 or
labctrl2
Chip-Wide Reset
D
Q
PRN
D
Q
CLRN
labctrl1 or
labctrl2
Chip-Wide Reset
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2.
Asynchronous Preset
An asynchronous preset is implemented with an asynchronous clear. The
Altera software provides preset control by using the clear and inverting
the input and output of the register. Inversion control is available for the
inputs to both LEs and IOEs. Therefore, this technique can be used when
a register drives logic or drives a pin.
In addition to the two clear and preset modes, FLEX 6000 devices provide
a chip-wide reset pin (DEV_CLRn) that can reset all registers in the device.
The option to use this pin is set in the Altera software before compilation.
The chip-wide reset overrides all other control signals. Any register with
an asynchronous preset will be preset when the chip-wide reset is asserted
because of the inversion technique used to implement the asynchronous
preset.
The Altera software can use a programmable NOT-gate push-back
technique to emulate simultaneous preset and clear or asynchronous load.
However, this technique uses an additional three LEs per register.
FastTrack Interconnect
In the FLEX 6000 OptiFLEX architecture, connections between LEs and
device I/O pins are provided by the FastTrack Interconnect, a series of
continuous horizontal and vertical routing channels that traverse the
device. This global routing structure provides predictable performance,
even for complex designs. In contrast, the segmented routing in FPGAs
requires switch matrices to connect a variable number of routing paths,
increasing the delays between logic resources and reducing performance.
Altera Corporation
17