EPF6024AQC240-2 Altera, EPF6024AQC240-2 Datasheet - Page 7
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EPF6024AQC240-2
Manufacturer Part Number
EPF6024AQC240-2
Description
IC FLEX 6000 FPGA 24K 240-PQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet
1.EPF6010ATC100-3N.pdf
(52 pages)
Specifications of EPF6024AQC240-2
Number Of Logic Elements/cells
1960
Number Of Labs/clbs
196
Number Of I /o
199
Number Of Gates
24000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-1286
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF6024AQC240-2
Manufacturer:
ALTERA
Quantity:
1 150
Part Number:
EPF6024AQC240-2
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2. Logic Array Block
Altera Corporation
LAB or IOEs
Adjacent
To/From
Local Interconnect
Row Interconnect
The interleaved LAB structure—an innovative feature of the FLEX 6000
architecture—allows each LAB to drive two local interconnects. This
feature minimizes the use of the FastTrack Interconnect, providing higher
performance. An LAB can drive 20 LEs in adjacent LABs via the local
interconnect, which maximizes fitting flexibility while minimizing die
size. See
In most designs, the registers only use global clock and clear signals.
However, in some cases, other clock or asynchronous clear signals are
needed. In addition, counters may also have synchronous clear or load
signals. In a design that uses non-global clock and clear signals, inputs
from the first LE in an LAB are re-routed to drive the control signals for
that LAB. See
The 10 LEs in the LAB are driven by two
local interconnect areas. The LAB can drive
two local interconnect areas.
Figure
The row interconnect is
bidirectionally connected
to the local interconnect.
Figure
2.
FLEX 6000 Programmable Logic Device Family Data Sheet
3.
LEs can directly drive the row
and column interconnect.
Column Interconnect
To/From
Adjacent
LAB or IOEs
7