EPF6024AQC240-2 Altera, EPF6024AQC240-2 Datasheet - Page 39
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EPF6024AQC240-2
Manufacturer Part Number
EPF6024AQC240-2
Description
IC FLEX 6000 FPGA 24K 240-PQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet
1.EPF6010ATC100-3N.pdf
(52 pages)
Specifications of EPF6024AQC240-2
Number Of Logic Elements/cells
1960
Number Of Labs/clbs
196
Number Of I /o
199
Number Of Gates
24000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-1286
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF6024AQC240-2
Manufacturer:
ALTERA
Quantity:
1 150
Part Number:
EPF6024AQC240-2
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
t
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t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
ZX1
ZX2
ZX3
IOE
IN
IN_DELAY
LOCAL
ROW
COL
DIN_D
DIN_C
LEGLOBAL
LABCARRY
LABCASC
Table 20. IOE Timing Microparameters
Table 21. Interconnect Timing Microparameters
Table 22. External Reference Timing Parameters
1
DRR
Symbol
Symbol
Symbol
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = on
Output buffer disable delay
Output buffer enable delay, slow slew rate = off, V
Output buffer enable delay, slow slew rate = off, V
IOE output buffer enable delay, slow slew rate = on
Output enable control delay
Input pad and buffer to FastTrack Interconnect delay
Input pad and buffer to FastTrack Interconnect delay with additional delay
turned on
LAB local interconnect delay
Row interconnect routing delay
Column interconnect routing delay
Dedicated input to LE data delay
Dedicated input to LE control delay
LE output to LE control via internally-generated global signal delay
Routing delay for the carry-out of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Register-to-register test pattern
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local
interconnects
Note (1)
FLEX 6000 Programmable Logic Device Family Data Sheet
Parameter
Parameter
Parameter
Note (1)
CCIO
CCIO
CCIO
CCIO
= V
= low voltage
= V
= low voltage
CCINT
CCINT
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
(5)
(5)
(5)
(6)
(7)
Conditions
Conditions
Conditions
(2)
(3)
(4)
(2)
(3)
(4)
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