EP4CE40F29C7N Altera, EP4CE40F29C7N Datasheet - Page 30
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CE40F29C7N
Manufacturer Part Number
EP4CE40F29C7N
Description
IC CYCLONE IV E FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29C7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2685
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE40F29C7N
Manufacturer:
ALTERA
Quantity:
852
Part Number:
EP4CE40F29C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
1–30
Table 1–33. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices
Preliminary
Table 1–34. True LVDS Transmitter Timing Specifications for Cyclone IV Devices
Cyclone IV Device Handbook, Volume 3
t
TCCS
Output jitter
(peak to peak)
t
t
t
Notes to
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) Cyclone IV E—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at
(3) t
(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
f
clock
frequency)
HSIODR
t
TCCS
Output jitter
(peak to peak)
DUTY
RISE
FALL
LOCK
HSCLK
DUTY
Symbol
Symbol
(3)
the output pin of all I/O banks.
Cyclone IV GX—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated mini-LVDS transmitter is supported at the
output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
LOCK
(input
Table
is the time required for the PLL to lock from the end-of-device configuration.
1–33:
20 – 80%,
C
20 – 80%,
C
Modes
LOAD
LOAD
×10
×10
Modes
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
—
—
—
= 5 pF
= 5 pF
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
Min Typ Max Min Typ
45
—
—
—
—
—
C6
500
500
—
—
—
—
C6
Max
420
420
420
420
420
420
840
840
840
840
840
420
200
500
55
200
500
55
—
—
1
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
45
—
—
—
—
—
C7, I7
C7, I7
500
500
—
—
—
—
402.5
402.5
Max
370
370
370
370
370
740
740
740
740
740
200
500
55
Max
200
500
55
—
—
1
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
Min Typ
45
—
—
—
—
—
C8, A7
C8, A7
500
500
—
—
—
—
402.5
402.5
Max
320
320
320
320
320
640
640
640
640
640
200
550
55
(Note
(Note 1)
Max
200
550
55
—
—
1
1),
Min
Chapter 1: Cyclone IV Device Datasheet
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
,
(3)
(2),
© December 2010 Altera Corporation
Min
C8L, I8L
45
—
—
—
—
—
(4)
(Part 1 of 2) —Preliminary
C8L, I8L
500
500
Typ
—
—
—
—
Max
320
320
320
320
320
362
640
640
640
640
640
362
200
600
55
(Part 2 of 2)—
Switching Characteristics
Max
200
600
55
—
—
1
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
Mi
45
—
—
—
—
—
C9L
n
Max
250
250
250
250
250
265
500
500
500
500
500
265
200
700
500
500
Typ
—
—
—
55
C9L
—
Max
200
700
55
—
—
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps
%
Unit
ms
%
ps
ps
ps
ps