EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 49

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Memory Blocks in Cyclone IV Devices
Memory Modes
Figure 3–12. Cyclone IV Devices Shift Register Mode Configuration
ROM Mode
FIFO Buffer Mode
© November 2009 Altera Corporation
f
w × m × n Shift Register
W
W
W
W
Figure 3–12
Cyclone IV devices M9K memory blocks support ROM mode. A .mif initializes the
ROM contents of these blocks. The address lines of the ROM are registered. The
outputs can be registered or unregistered. The ROM read operation is identical to the
read operation in the single-port RAM configuration.
Cyclone IV devices M9K memory blocks support single-clock or dual-clock FIFO
buffers. Dual clock FIFO buffers are useful when transferring data from one clock
domain to another clock domain. Cyclone IV devices M9K memory blocks do not
support simultaneous read and write from an empty FIFO buffer.
For more information about FIFO buffers, refer to the
Megafunction User
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
shows the Cyclone IV devices M9K memory block in shift register mode.
Guide.
W
W
W
W
Single- and Dual-Clock FIFO
Cyclone IV Device Handbook, Volume 1
n Number of Taps
3–13