EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 100
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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PLLs & Clock Networks
Figure 2–51. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
Notes to
(1)
(2)
(3)
(4)
2–86
Stratix Device Handbook, Volume 1
PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs.
CLK4, CLK6, CLK12, and CLK14 feed the corresponding PLL’s inclk0 port.
CLK5, CLK7, CLK13, and CLK15 feed the corresponding PLL’s inclk1 port.
The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11 and 12.
Figure
Regional
Regional
Clocks
Clocks
2–51:
Clocks
Global
RCLK2
RCLK3
RCLK6
RCLK7
L0 L1 G0 G1 G2 G3
L0 L1 G0 G1 G2 G3
E[0..3]
PLL 6
PLL 5
(1)
(2)
(2)
(1)
G0 G1 G2 G3 L0 L1
G0 G1 G2 G3 L0 L1
(1)
PLL 11
(1)
PLL 12
(2)
(2)
RCLK10
RCLK11
G12
G13
G14
G15
G4
G5
G6
G7
RCLK12
RCLK13
Altera Corporation
Note (1)
July 2005
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