EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 235
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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Figure 4–8. Measurement Setup for T
Altera Corporation
January 2006
Notes to
(1)
(2)
(3)
(4)
3.3-V CTT
Table 4–102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 2 of 2)
Notes
Input measurement point at internal node is 0.5 × V
Output measuring point for data is V
rising edge and the other is for the falling edge.
Input stimulus edge rate is 0 to V
The first value is for the output rising edge and the second value is for the output falling edge. The hyphen (-)
indicates infinite resistance or disconnection.
I/O Standard
(1), (2),
Table
CLK
OUT
OUT
4–102:
(3)
R
T
Ω
–
Figure 4–8
enable timing. The T
same as T
is the same as T
UP
CHZ
T
CLZ
CCINT
R
XZ
Ω
–
DN
MEAS
and T
XZ
in 0.5 ns (internal signal) from the driver preceding the I/O buffer.
shows the measurement setup for output disable and output
. The T
. When two values are given, the first is the measurement point on the
Loading and Termination
ZX
R
25
Ω
ZX
S
.
CLZ
CHZ
CCINT
50
stands for clock to low Z (driving) time delay and
R
Ω
T
stands for clock to high Z time delay and is the
.
200mV
200mV
200mV
200mV
3.600
V
(V)
CCIO
Stratix Device Handbook, Volume 1
1.650
VTT
(V)
DC & Switching Characteristics
V
(pF)
T
30
C
C
=1.5V
L
TOTAL
R =50
=10pF
Measurement
Ω
V
1.650
Point
MEAS
4–65
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