EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 197
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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Figure 4–3. Dual-Port RAM Timing Microparameter Waveform
Altera Corporation
January 2006
unreg_data-out
reg_data-out
wraddress
rdaddress
rdclock
data-in
wrclock
wren
rden
doutn-2
an-1
din-1
t
t
DATASU
WERESU
doutn-1
bn
t
DATAH
an
din
Figure 4–3
and M-RAM timing parameters shown in
Internal timing parameters are specified on a speed grade basis
independent of device density.
internal timing microparameters for LEs, IOEs, TriMatrix memory
structures, DSP blocks, and MultiTrack interconnects.
t
t
t
R4
R8
R24
Table 4–43. Routing Delay Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
t
doutn-1
WEREH
doutn
a0
b0
shows the TriMatrix memory waveforms for the M512, M4K,
Delay for an R4 line with average loading; covers a distance of four
LAB columns.
Delay for an R8 line with average loading; covers a distance of eight
LAB columns.
Delay for an R24 line with average loading; covers a distance of 24
LAB columns.
t
t
DATACO1
WEREH
t
DATACO2
a1
t
RC
doutn
dout0
a2
b1
Tables 4–44
Parameter
t
t
WADDRSU
Stratix Device Handbook, Volume 1
a3
WERESU
dout0
Tables 4–40
DC & Switching Characteristics
through
din4
a4
b2
4–50
through 4–42.
t
WADDRH
show the
din5
a5
b3
din6
a6
4–27
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