EP1S20F484C7 Altera, EP1S20F484C7 Datasheet - Page 57

• Manufacturer Part Number: EP1S20F484C7
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 361
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1101

Altera Corporation
July 2005
Table 2–12
column units (B1 to B6 and A1 to A6). It also shows the address and
control signal input connections to the row units (R1 to R11).
Table 2–12. M-RAM Row & Column Interface Unit Signals
Unit Interface Block
R10
R11
R1
R2
R3
R4
R5
R6
R7
R8
R9
B1
B2
B3
B4
B5
B6
A1
A2
A3
A4
A5
A6
shows the input and output data signal connections for the
byte_enable_a[7..0]
byte_enable_b[7..0]
datain_b[71..60]
datain_b[59..48]
datain_b[47..36]
datain_b[35..24]
datain_b[23..12]
datain_a[71..60]
datain_a[59..48]
datain_a[47..36]
datain_a[35..24]
datain_a[23..12]
addressa[15..8]
addressb[15..8]
datain_b[11..0]
datain_a[11..0]
addressa[7..0]
addressb[7..0]
Input SIgnals
clocken_a
clocken_b
renwe_a
renwe_b
clock_a
clock_b
-
-
-
-
Stratix Device Handbook, Volume 1
dataout_b[71..60]
dataout_b[59..48]
dataout_b[47..36]
dataout_b[35..24]
dataout_b[23..12]
dataout_a[71..60]
dataout_a[59..48]
dataout_a[47..36]
dataout_a[35..24]
dataout_a[23..12]
Stratix Architecture
dataout_b[11..0]
dataout_a[11..0]
Output Signals
2–43