EP1S20F484C7 Altera, EP1S20F484C7 Datasheet - Page 99

IC STRATIX FPGA 20K LE 484-FBGA

EP1S20F484C7

Manufacturer Part Number
EP1S20F484C7
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F484C7

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
361
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1101

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0
Figure 2–50. Global & Regional Clock Connections from Side Pins & Fast PLL Outputs
Notes to
(1)
(2)
Altera Corporation
July 2005
FPLL7CLK
FPLL8CLK
CLK1
CLK2
CLK3
CLK0
PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs.
The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A pin or other PLL must drive
the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
Figure
2–50:
PLL 7
PLL 1
PLL 2
PLL 8
g0
g0
g0
g0
l0
l1
l0
l1
l0
l1
l0
l1
2
Figure 2–50
and the CLK pins.
Figure 2–51
outputs and top CLK pins.
Regional
Clocks
shows the global and regional clocking from the PLL outputs
shows the global and regional clocking from enhanced PLL
Global
Clocks
Regional
Clocks
Stratix Device Handbook, Volume 1
2
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
PLL 10
PLL 4
PLL 3
PLL 9
Note
Stratix Architecture
(1),
(2)
FPLL10CLK
CLK10
CLK11
CLK8
CLK9
FPLL9CLK
2–85

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