EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 78
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EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
1–70
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
t
differential I/O
standards with one
external output resistor
network
t
t
TCCS
Receiver
True differential I/O
standards - f
(data rate)
f
DPA run length
Soft-CDR PPM
tolerance
DUTY
RISE &
HSDR
x Jitter
(data rate)
-
t
Symbol
FALL
emulated
HSDRDPA
SERDES factor J = 2,
SERDES factor J = 1,
uses an SDR register
TX output clock duty
Emulated differential
three external output
Emulated differential
True differential I/O
one external output
uses DDR registers
cycle for both True
I/O standards with
I/O standards with
resistor networks
Soft-CDR mode
SERDES factor
SERDES factor
differential I/O
and emulated
LVDS_E_3R
Conditions
J = 3 to 10
J = 3 to 10
True LVDS
DPA mode
standards
standards
Emulated
resistor
—
Min
150
—
45
—
—
—
—
—
—
—
(4)
(4)
(4)
C3, I3
Typ
—
50
—
—
—
—
—
—
—
—
—
—
—
(Note 1), (2), (10)
10000
1250
Max
0.15
200
250
500
100
250
300
55
(6)
(4)
(4)
Chapter 1: Device Datasheet for Arria II Devices
Min
150
—
45
—
—
—
—
—
—
—
(4)
(4)
(4)
(Part 2 of 3)
December 2010 Altera Corporation
C4, I4
Typ
—
50
—
—
—
—
—
—
—
—
—
—
—
Switching Characteristics
10000
1250
Max
0.15
200
300
500
100
250
300
55
(6)
(4)
(4)
± PPM
Mbps
Mbps
Mbps
Mbps
Unit
UI
ps
ps
ps
ps
ps
UI
%