EP1S25F672I7N Altera, EP1S25F672I7N Datasheet - Page 134
![IC STRATIX FPGA 25K LE 672-FBGA](/photos/6/73/67394/ds-672fbga205-2_0_sml.jpg)
EP1S25F672I7N
Manufacturer Part Number
EP1S25F672I7N
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F672I7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
473
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F672I7N
Manufacturer:
ALTERA
Quantity:
624
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I/O Structure
2–120
Stratix Device Handbook, Volume 1
Table 2–28
strength control.
Quartus II software version 4.2 and later will report current strength as
“PCI Compliant” for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact PCI I/O
standards.
Stratix devices support series on-chip termination (OCT) using
programmable drive strength. For more information, contact your Altera
Support Representative.
Open-Drain Output
Stratix devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
Slew-Rate Control
The output buffer for each Stratix device I/O pin has a programmable
output slew-rate control that can be configured for low-noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may
introduce noise transients into the system. A slow slew rate reduces
system noise, but adds a nominal delay to rising and falling edges. Each
Notes to
(1)
(2)
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
GTL/GTL+
1.5-V HSTL Class I and II
1.8-V HSTL Class I and II
SSTL-3 Class I and II
SSTL-2 Class I and II
SSTL-18 Class I and II
Table 2–28. Programmable Drive Strength
This is the Quartus II software default current setting.
I/O banks 1, 2, 5, and 6 do not support this setting.
Table
I/O Standard
shows the possible settings for the I/O standards with drive
2–28:
24 (1), 16, 12, 8, 4
24 (2), 12 (1), 8, 4, 2
16 (1), 12, 8, 2
12 (1), 8, 2
8 (1), 4, 2
Support max and min strength
I
OH
/ I
OL
Current Strength Setting (mA)
Altera Corporation
July 2005
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