EP1S25F672I7N Altera, EP1S25F672I7N Datasheet - Page 230
![IC STRATIX FPGA 25K LE 672-FBGA](/photos/6/73/67394/ds-672fbga205-2_0_sml.jpg)
EP1S25F672I7N
Manufacturer Part Number
EP1S25F672I7N
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F672I7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
473
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F672I7N
Manufacturer:
ALTERA
Quantity:
624
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Timing Model
4–60
Stratix Device Handbook, Volume 1
Skew on Input Pins
Table 4–99
worst case I/O skew value. You can use these values, for example, when
calculating the timing budget on the input (read) side of a memory
interface.
PLL Counter & Clock Network Skews
Table 4–100
the Stratix device PLL.
I/O Timing Measurement Methodology
Different I/O standards require different baseline loading techniques for
reporting timing delays. Altera characterizes timing delays with the
required termination and loading for each I/O standard. The timing
information is specified from the input clock pin up to the output pin of
Note to
(1)
Pins in the same I/O bank
Pins in top/bottom (vertical I/O) banks
Pins in left/right side (horizontal I/O) banks
Pins across the entire device
Clock skew between two external clock outputs driven
by the same counter
Clock skew between two external clock outputs driven
by the different counters with the same settings
Dual-purpose PLL dedicated clock output used as I/O
pin vs. regular I/O pin
Clock skew between any two outputs of the PLL that
drive global clock networks
Table 4–99. Package Skew on Input Pins
Table 4–100. PLL Counter & Clock Network Skews
The Quartus II software models 270 ps of delay on the PLL dedicated clock
output (PLL6_OUT[3..0]p/n and PLL5_OUT[3..0]p/n) pins both when
used as clocks and when used as I/O pins.
Table
shows the package skews that were considered to get the
shows the clock skews between different clock outputs from
4–100:
Package Parameter
Parameter
Worst-Case Skew (ps)
Worst-Case Skew (ps)
Altera Corporation
270
100
50
50
50
100
150
150
January 2006
(1)
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