EP1S30F780C7 Altera, EP1S30F780C7 Datasheet - Page 112
![IC STRATIX FPGA 30K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S30F780C7
Manufacturer Part Number
EP1S30F780C7
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S30F780C7
Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1421
EP1S30SF780C7
EP1S30SF780C7
Available stocks
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Manufacturer
Quantity
Price
Part Number:
EP1S30F780C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Part Number:
EP1S30F780C7N
Manufacturer:
ALTERA30
Quantity:
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Part Number:
EP1S30F780C7N
Manufacturer:
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PLLs & Clock Networks
2–98
Stratix Device Handbook, Volume 1
f
The variation due to process, voltage, and temperature is about ±15% on
the delay settings. PLL reconfiguration can control the clock delay shift
elements, but not the VCO phase shift multiplexers, during system
operation.
Spread-Spectrum Clocking
Stratix device enhanced PLLs use spread-spectrum technology to reduce
electromagnetic interference generation from a system by distributing the
energy over a broader frequency range. The enhanced PLL typically
provides 0.5% down spread modulation using a triangular profile. The
modulation frequency is programmable. Enabling spread-spectrum for a
PLL affects all of its outputs.
Lock Detect
The lock output indicates that there is a stable clock output signal in
phase with the reference clock. Without any additional circuitry, the lock
signal may toggle as the PLL begins tracking the reference clock. You may
need to gate the lock signal for use as a system control. The lock signal
from the locked port can drive the logic array or an output pin.
Whenever the PLL loses lock (for example, inclk jitter, clock switchover,
PLL reconfiguration, power supply noise, and so on), the PLL must be
reset with the areset signal to guarantee correct phase relationship
between the PLL output clocks. If the phase relationship between the
input clock versus output clock, and between different output clocks
from the PLL is not important in the design, then the PLL need not be
reset.
See the Stratix FPGA Errata Sheet for more information on implementing
the gated lock signal in a design.
Programmable Duty Cycle
The programmable duty cycle allows enhanced PLLs to generate clock
outputs with a variable duty cycle. This feature is supported on each
enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle
setting is achieved by a low and high time count setting for the post-scale
dividers. The Quartus II software uses the frequency input and the
required multiply or divide rate to determine the duty cycle choices.
Advanced Clear & Enable Control
There are several control signals for clearing and enabling PLLs and their
outputs. You can use these signals to control PLL resynchronization and
gate PLL output clocks for low-power applications.
Altera Corporation
July 2005
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