EP1S25F672I7 Altera, EP1S25F672I7 Datasheet - Page 147
![IC STRATIX FPGA 25K LE 672-FBGA](/photos/6/74/67411/ep1s25f672i7_sml.jpg)
EP1S25F672I7
Manufacturer Part Number
EP1S25F672I7
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F672I7
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
473
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2087
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F672I7N
Manufacturer:
ALTERA
Quantity:
624
- Current page: 147 of 276
- Download datasheet (4Mb)
Altera Corporation
July 2005
780-pin
FineLine
BGA
956-pin
BGA
1,020-pin
FineLine
BGA
780-pin
FineLine
BGA
Table 2–38. EP1S30 Differential Channels
Table 2–39. EP1S40 Differential Channels (Part 1 of 2)
Package
Package
Transmitter/
Transmitter
(4)
Receiver
Transmitter
(4)
Receiver
Transmitter
(4)
Receiver
Transmitter
(4)
Receiver
Transmitter
/Receiver
Receiver
70
66
80
80
80 (2)
80 (2)
Channels
68
66
Channels
The only way you can use the rx_data_align is if one of the following
is true:
■
■
Total
Total
(7)
(7)
The receiver PLL is only clocking receive channels (no resources for
the transmitter)
If all channels can fit in one I/O bank
840
840
840
840
840
840
840
840
840
840
840
840
840
840
840
840
Maximum
Maximum
(Mbps)
Speed
(Mbps)
Speed
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
Note (1)
,
,
(8)
(8)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
(1)
(1)
18
34
17
33
18
35
17
33
19
39
20
40
19
39
20
40
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
Center Fast PLLs
Center Fast PLLs
Note (1)
(1)
17
35
16
33
20
39
20
40
20
39
20
40
16
34
16
33
(1)
16
34
16
33
17
35
16
33
20
39
20
40
20
39
20
40
Stratix Device Handbook, Volume 1
(1)
(1)
18
35
17
33
19
39
20
40
19
39
20
40
18
34
17
33
19 (1)
19 (1)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
20
20
19
19
20
20
Corner Fast PLLs (2),
Corner Fast PLLs (2),
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
20
20
20
20
20
20
20
20
Stratix Architecture
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
20
20
20
20
20
20
20
20
(6)
(6)
(6)
(6)
19 (1)
19 (1)
2–133
(3)
(6)
(6)
(6)
(6)
20
20
19
19
20
20
(3)
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