EP1S25F672I7 Altera, EP1S25F672I7 Datasheet - Page 176

• Manufacturer Part Number: EP1S25F672I7
• Description: IC STRATIX FPGA 25K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S25F672I7

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 473
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 473
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2087

Operating Conditions
4–6
Stratix Device Handbook, Volume 1
V
V
Table 4–10. 3.3-V LVDS I/O Specifications (Part 1 of 2)
CCIO
ID
Symbol
(6)
I/O supply voltage
Input differential voltage
swing (single-ended)
Parameter
Figure 4–2. Transmitter Output Waveforms for Differential I/O Standards
Tables 4–10
DC operating conditions, and capacitance for 1.5-V Stratix
devices.
Single-Ended Waveform
Differential Waveform
0.1 V ≤ V
W = 1 through 10
1.1 V ≤ V
W = 1
1.1 V ≤ V
W = 2 through10
1.6 V < V
W = 1 through 10
through
V
CM
Conditions
V
CM
CM
CM
OD
CM
4–33
< 1.1 V
≤ 1.6 V
≤ 1.6 V
≤ 1.8 V
recommend operating conditions,
V
OD
Minimum
3.135
300
200
100
300
Typical
3.3
V
OD
p − n = 0 V
Positive Channel (p) = V
Negative Channel (n) = V
Ground
Maximum
Altera Corporation
3.465
1,000
1,000
1,000
1,000
January 2006
Unit
mV
mV
mV
mV
V
OH
OL