EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 105
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
October 2007
The Stratix II GX clock networks can be disabled (powered down) by both
static and dynamic approaches. When a clock net is powered down, all
the logic fed by the clock net is in an off-state, thereby reducing the overall
power consumption of the device. The global and regional clock
networks can be powered down statically through a setting in the
configuration file (.sof or .pof). Clock networks that are not used are
automatically powered down through configuration bit settings in the
configuration file generated by the Quartus II software. The dynamic
clock enable and disable feature allows the internal logic to control power
up and down synchronously on GCLK and RCLK nets and PLL_OUT pins.
This function is independent of the PLL and is applied directly on the
clock network or PLL_OUT pin, as shown in
Enhanced and Fast PLLs
Stratix II GX devices provide robust clock management and synthesis
using up to four enhanced PLLs and four fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock frequency
synthesis. With features such as clock switchover, spread spectrum
clocking, reconfigurable bandwidth, phase control, and reconfigurable
phase shifting, the Stratix II GX device’s enhanced PLLs provide you with
complete control of clocks and system timing. The fast PLLs provide
general purpose clocking with multiplication and phase shifting as well
as high-speed outputs for high-speed differential I/O support. Enhanced
and fast PLLs work together with the Stratix II GX high-speed I/O and
advanced clock architecture to provide significant improvements in
system performance and bandwidth.
Stratix II GX Device Handbook, Volume 1
Figures 2–67
Stratix II GX Architecture
through 2–69.
2–97
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