EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 243
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
June 2009
(1)
(2)
(3)
t
t
t
t
t
t
t
t
t
t
t
M512CLR
M4KRC
M4KWERESU
M4KWEREH
M4KBESU
M4KBEH
M4KDATAASU
M4KDATAAH
M4KADDRASU
M4KADDRAH
M4KDATABSU
Table 4–59. M512 Block Internal Timing Microparameters (Part 2 of 2)
Table 4–60. M4K Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Symbol
The M512 block f
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Synchronous
read cycle time
Write or read
enable setup
time before clock
Write or read
enable hold time
after clock
Byte enable
setup time before
clock
Byte enable hold
time after clock
A port data setup
time before clock
A port data hold
time after clock
A port address
setup time before
clock
A port address
hold time after
clock
B port data setup
time before clock
Minimum clear
pulse width
Parameter
Parameter
MAX
obtained using the Quartus II software does not necessarily equal to 1/TM512RC.
-3 Speed Grade
144
1462
Min
Min
203
203
203
203
22
22
22
22
22
-3 Speed
Grade(2)
(2)
Max
Max
2240
-3 Speed Grade
-3 Speed Grade
151
1462
Min
Min
213
213
213
213
23
23
23
23
23
(3)
(3)
Max
Max
2351
Stratix II GX Device Handbook, Volume 1
-4 Speed Grade -5 Speed Grade
-4 Speed Grade -5 Speed Grade
160
1462
Min
Min
226
226
226
226
24
24
24
24
24
DC and Switching Characteristics
Note (1)
Max
Max
2500
192
Min
1462
Min
272
272
272
272
29
29
29
29
29
Max
Max
3000
Unit
Unit
4–73
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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