EP2SGX60EF1152I4N Altera, EP2SGX60EF1152I4N Datasheet - Page 117

• Manufacturer Part Number: EP2SGX60EF1152I4N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2187

Figure 2–74. Stratix II GX Enhanced PLL
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
October 2007
Global or
Regional
Clock
INCLK[3..0]
Each clock source can come from any of the four clock pins that are physically located on the same side of the device
as the PLL.
If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin.
Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Figure
4
Shaded Portions of the
PLL are Reconfigurable
2–74:
FBIN
Switchover
Circuitry
Clock
(2)
Enhanced PLLs
Stratix II GX devices contain up to four enhanced PLLs with advanced
clock management features. These features include support for external
clock feedback mode, spread-spectrum clocking, and counter cascading.
Figure 2–74
Fast PLLs
Stratix II GX devices contain up to four fast PLLs with high-speed serial
interfacing ability. The fast PLLs offer high-speed outputs to manage the
high-speed differential I/O interfaces.
the fast PLL.
/n
Phase Frequency
Detector
PFD
shows a diagram of the enhanced PLL.
Charge
Pump
Note (1)
Lock Detect
& Filter
Spectrum
/m
Spread
Loop
Filter
VCO Phase Selection
Affecting All Outputs
VCO Phase Selection
Selectable at Each
PLL Output Port
VCO
Stratix II GX Device Handbook, Volume 1
8
Figure 2–75
Post-Scale
Counters
/c0
/c1
/c2
/c3
/c4
/c5
From Adjacent PLL
6
Stratix II GX Architecture
shows a diagram of
4
8
6
Global
Clocks
Regional
Clocks
I/O Buffers (3)
to I/O or general
routing
2–109