EP2SGX60EF1152I4N Altera, EP2SGX60EF1152I4N Datasheet - Page 162

• Manufacturer Part Number: EP2SGX60EF1152I4N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2187

Configuration
3–6
Stratix II GX Device Handbook, Volume 1
FPP
AS
PS
PPA
Configuration
Table 3–4. Stratix II GX Configuration Features (Part 1 of 2)
Scheme
MAX II device or microprocessor and
flash device
Enhanced configuration device
Serial configuration device
MAX II device or microprocessor and
flash device
Enhanced configuration device
Download cable
MAX II device or microprocessor and
flash device
f
Configuration Method
Configuration Schemes
You can load the configuration data for a Stratix II GX device with one of
five configuration schemes (refer to
target application. You can use a configuration device, intelligent
controller, or the JTAG port to configure a Stratix II GX device. A
configuration device can automatically configure a Stratix II GX device at
system power-up.
Multiple Stratix II GX devices can be configured in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device. Stratix II GX
FPGAs offer the following:
■
■
■
Table 3–4
configuration scheme.
Refer to the
volume 2 of the Stratix II GX Device Handbook for more information about
configuration schemes in Stratix II GX devices.
(4)
Configuration data decompression to reduce configuration file
storage
Design security using configuration data encryption to protect
designs
Remote system upgrades for remotely updating Stratix II GX designs
summarizes which configuration features can be used in each
Configuring Stratix II & Stratix II GX Devices
Design Security Decompression
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Table
3–4), chosen on the basis of the
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Altera Corporation
chapter in
Remote System
October 2007
Upgrade
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