EP1S40F1020I6 Altera, EP1S40F1020I6 Datasheet - Page 82

• Manufacturer Part Number: EP1S40F1020I6
• Description: IC STRATIX FPGA 40K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40F1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 773
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1862; EP1S40F1020I6

Digital Signal Processing Block
2–68
Stratix Device Handbook, Volume 1
single DSP block can implement two sums or differences from two
18 × 18-bit multipliers each or four sums or differences from two 9 × 9-bit
multipliers each.
You can use the two-multipliers adder mode for complex multiplications,
which are written as:
The two-multipliers adder mode allows a single DSP block to calculate
the real part [(a × c) – (b × d)] using one subtractor and the imaginary part
[(a × d) + (b × c)] using one adder, for data widths up to 18 bits. Two
complex multiplications are possible for data widths up to 9 bits using
four adder/subtractor/accumulator blocks.
two-multipliers adder.
Figure 2–38. Two-Multipliers Adder Mode Implementing Complex Multiply
Four-Multipliers Adder Mode
In the four-multipliers adder mode, the DSP block adds the results of two
first -stage adder/subtractor blocks. One sum of four 18 × 18-bit
multipliers or two different sums of two sets of four 9 × 9-bit multipliers
can be implemented in a single DSP block. The product width for each
multiplier must be the same size. The four-multipliers adder mode is
useful for FIR filter applications.
adder mode.
(a + jb) × (c + jd) = [(a × c) – (b × d)] + j × [(a × d) + (b × c)]
18
18
18
18
A
C
B
D
A
D
B
C
18
18
18
18
18
18
18
18
36
36
36
36
Figure 2–39
Subtractor
Adder
DSP Block
Figure 2–38
shows the four multipliers
37
37
(Imaginary Part)
(A × C) − (B × D)
(A × D) + (B × C)
(Real Part)
Altera Corporation
shows an 18-bit
July 2005