EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 175

• Manufacturer Part Number: EP1SGX40GF1020I6
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
February 2005
Notes to
(1)
(2)
(3)
EP1SGX10
EP1SGX25
EP1SGX40
Table 4–23. DQS & DQ Bus Mode Support
Device
See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook,
Volume 2 for V
These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8.
These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8.
Table
672-pin FineLine BGA
672-pin FineLine BGA
1,020-pin FineLine BGA
1,020-pin FineLine BGA
4–23:
REF
guidelines.
Package
Table 4–23
per device.
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and clocks DQ input registers with the DQS signal.
Two separate single phase-shifting reference circuits are located on the
top and bottom of the Stratix GX device. Each circuit is driven by a system
reference clock through the CLK pins that is the same frequency as the
DQS signal. Clock pins CLK[15..12]p feed the phase-shift circuitry on
the top of the device and clock pins CLK[7..4]p feed the phase-shift
circuitry on the bottom of the device. The phase-shifting reference circuit
on the top of the device controls the compensated delay elements for all
10 DQS pins located at the top of the device. The phase-shifting reference
circuit on the bottom of the device controls the compensated delay
elements for all 10 DQS pins located on the bottom of the device. All
10 delay elements (DQS signals) on either the top or bottom of the device
shift by the same degree amount. For example, all 10 DQS pins on the top
of the device can be shifted by 90° and all 10 DQS pins on the bottom of
the device can be shifted by 72°. The reference circuits require a maximum
of 256 system reference clock cycles to set the correct phase on the DQS
delay elements.
control of each DQS delay shift on the top of the device. This same circuit
is duplicated on the bottom of the device.
shows the number of DQ and DQS buses that are supported
Figure 4–68
Note (1)
Number of ×8
Groups
12
16
20
20
(2)
(3)
illustrates the phase-shift reference circuit
Number of ×16
Stratix GX Device Handbook, Volume 1
Groups
0
8
8
8
Stratix GX Architecture
Number of ×32
Groups
0
4
4
4
4–109