EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 183

no-image

EP1SGX40GF1020I6

Manufacturer Part Number
EP1SGX40GF1020I6
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX40GF1020I6

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
41250
# I/os (max)
624
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX40GF1020I6
Manufacturer:
ALTERA
Quantity:
1 238
Part Number:
EP1SGX40GF1020I6
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1SGX40GF1020I6
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1SGX40GF1020I6
Manufacturer:
ALTERA
0
Part Number:
EP1SGX40GF1020I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1SGX40GF1020I6N
Manufacturer:
XILINX
0
Part Number:
EP1SGX40GF1020I6N
Manufacturer:
ALTERA
0
Altera Corporation
February 2005
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL (clock
inputs)
Differential HSTL (clock
outputs)
Differential SSTL (clock
outputs)
3.3-V GTL
3.3-V GTL+
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
SSTL-18 class I
SSTL-18 class II
SSTL-2 class I
SSTL-2 class II
SSTL-3 class I
Table 4–28. I/O Support by Bank (Part 1 of 2)
I/O Standard
Table 4–28
Top & Bottom Banks
(3, 4, 7 & 8)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
shows I/O standard support for each I/O bank.
Left Banks
(1 & 2)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Stratix GX Device Handbook, Volume 1
Enhanced PLL External
Stratix GX Architecture
Clock Output Banks
(9, 10, 11 & 12)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
4–117

Related parts for EP1SGX40GF1020I6