EP2SGX90FF1508C3N Altera, EP2SGX90FF1508C3N Datasheet - Page 296

• Manufacturer Part Number: EP2SGX90FF1508C3N
• Description: IC STRATIX II GX 90K 1508-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90FF1508C3N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 650
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1508-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1772; EP2SGX90FF40C3N; EP2SGX90FF40C3NES

High-Speed I/O Specifications
High-Speed I/O
Specifications
4–126
Stratix II GX Device Handbook, Volume 1
t
f
J
W
t
t
Timing unit interval (TUI)
f
f
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter
Output jitter
t
t
C
H S C L K
R I S E
F A L L
IN
H S D R
H S D R D P A
DUTY
L O C K
Table 4–106. High-Speed Timing Specifications and Definitions
High-Speed Timing Specifications
Table 4–106
1.2-V HSTL
LVPECL
Column DDIO Output I/O
Table 4–105. Maximum DCD for DDIO Output on Column I/O Pins With PLL in
the Clock Path (Part 2 of 2)
Maximum DCD (ps) for
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t
Fast PLL input clock frequency
Maximum/minimum LVDS data transfer rate (f
Maximum/minimum LVDS data transfer rate (f
The timing difference between the fastest and the slowest output edges
including t
same fast PLL. The clock is included in the TCCS measurement.
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Standard
provides high-speed timing specifications definitions.
CO
variation and clock skew across channels driven by the
Stratix-II Devices (PLL Output Feeding
C
/w).
-3 Device
180
155
Definitions
DDIO)
-4 and -5 Device
H S D R
H S D R D PA
180
= 1/TUI), non-DPA.
155
Altera Corporation
= 1/TUI), DPA.
October 2007
Unit
ps
ps