EP2SGX90FF1508C3N Altera, EP2SGX90FF1508C3N Datasheet - Page 64

IC STRATIX II GX 90K 1508-FBGA

EP2SGX90FF1508C3N

Manufacturer Part Number
EP2SGX90FF1508C3N
Description
IC STRATIX II GX 90K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90FF1508C3N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
650
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1508-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1772
EP2SGX90FF40C3N
EP2SGX90FF40C3NES

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90FF1508C3N
Manufacturer:
ALTERA30
Quantity:
121
Part Number:
EP2SGX90FF1508C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX90FF1508C3N
Manufacturer:
ALTERA
0
Adaptive Logic Modules
Figure 2–41. ALM in Arithmetic Mode
2–56
Stratix II GX Device Handbook, Volume 1
datae0
datae1
dataf0
dataf1
datab
dataa
datad
datac
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder’s carry output along with combinational logic outputs.
In this operation, the adder output is ignored. This usage of the adder
with the combinational logic output provides resource savings of up to
50% for functions that can use this ability. An example of such
functionality is a conditional operation, such as the one shown in
Figure
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract ‘Y’ from ‘X’. If
‘X’ is less than ‘Y’, the carry_out signal will be ‘1’. The carry_out
signal is fed to an adder where it drives out to the LAB local interconnect.
It then feeds to the LAB-wide syncload signal. When asserted,
syncload selects the syncdata input. In this case, the data ‘Y’ drives
the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y’,
the syncload signal is de-asserted and ‘X’ drives the data port of the
registers.
4-Input
4-Input
4-Input
4-Input
2–42. The equation for this example is:
LUT
LUT
LUT
LUT
carry_out
carry_in
adder0
adder1
D
D
reg0
reg1
Q
Q
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
Altera Corporation
October 2007

Related parts for EP2SGX90FF1508C3N