EP4SE530H35C3 Altera, EP4SE530H35C3 Datasheet - Page 68
EP4SE530H35C3
Manufacturer Part Number
EP4SE530H35C3
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 68 of 1154
- Download datasheet (32Mb)
3–12
Figure 3–10. Simple Dual-Port Timing Waveforms
Figure 3–11. Mixed-Port Read-During-Write Timing Waveforms
Stratix IV Device Handbook Volume 1
q (asynch)
q (asynch)
wraddress
wraddress
rdaddress
rdaddress
wrclock
wrclock
rdclock
rdclock
wren
data
wren
data
rden
rden
din-1
doutn-1
din-1
doutn-1
an-1
an-1
Figure 3–10
dual-port mode with unregistered outputs. Registering the RAM outputs simply
delays the q output by one clock cycle.
Figure 3–11
mode with unregistered outputs.
bn
bn
an
an
din
din
shows timing waveforms for read and write operations in mixed-port
shows timing waveforms for read and write operations in simple
doutn
doutn
b0
b0
a0
a0
a1
a1
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
dout0
dout0
a2
b1
a2
b1
a3
a3
din4
din4
b2
b2
a4
a4
February 2011 Altera Corporation
din5
din5
a5
a5
b3
b3
a6
a6
din6
din6
Memory Modes
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