EP4SE530H35C3 Altera, EP4SE530H35C3 Datasheet - Page 865
EP4SE530H35C3
Manufacturer Part Number
EP4SE530H35C3
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4SE530H35C3ES
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP4SE530H35C3N
Manufacturer:
ALTERA
Quantity:
586
Company:
Part Number:
EP4SE530H35C3NES
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4SE530H35C3NES
Manufacturer:
ALTERA
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 865 of 1154
- Download datasheet (32Mb)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Table 5–5. Transceiver Channel Reconfiguration Modes and .mif Requirements
February 2011 Altera Corporation
Channel and CMU PLL
reconfiguration
Channel reconfiguration with
transmitter PLL select
Central control unit
reconfiguration
Data rate division in transmitter
Note to
(1) Because the transmitter local divider is not available for bonded mode channels, data rate division is supported for non-bonded channels only.
(2) Dynamic reconfiguration from a bonded mode with rate matcher to another bonded mode without rate matcher is not allowed.
Dynamic Reconfiguration
Table
Transceiver Channel Reconfiguration Mode Details
5–5:
Mode
1
(2)
The read transaction in Method 3 is identical to that in Method 2. Refer to
Transaction” on page
Table 5–5
reconfiguration modes available in the ALTGX_RECONFIG MegaWizard Plug-In
Manager.
You cannot dynamically reconfigure from Deterministic Latency mode with the
Enable PLL phase frequency detector (PFD) feedback to compensate latency
uncertainty in Tx dataout and Tx clkout paths relative to the reference clock option
enabled to any other mode with this option disabled. For instance, you cannot
dynamically reconfigure from a CPRI mode to a non-CPRI mode. You can
dynamically change the data rate for CPRI mode.
Read Transaction
lists the supported configurations for the various transceiver channel
Non-bonded configurations of
regular transceiver channels
All configurations of regular
configurations of regular
Basic (PMA Direct) ×1
Basic (PMA Direct) ×N
Basic (PMA Direct) ×1
Basic (PMA Direct) ×N
transceiver channels
transceiver channels
All Transmitter only
×4 bonded mode
×8 bonded mode
configuration
configuration
configuration
configuration
5–16.
To
Supported Configurations
Non-bonded configurations of
regular transceiver channels
All configurations of regular
configurations of regular
transceiver channels
Basic (PMA Direct) ×N
Basic (PMA Direct) ×N
Basic (PMA Direct) ×1
Basic (PMA Direct) ×1
transceiver channels
All Transmitter only
×4 bonded mode
×8 bonded mode
configuration
configuration
configuration
configuration
Stratix IV Device Handbook Volume 2: Transceivers
From
(1)
.mif Requirements
“Read
v
v
v
v
v
v
v
v
—
5–19
Related parts for EP4SE530H35C3
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: