EP4SE530H35C3 Altera, EP4SE530H35C3 Datasheet - Page 693
EP4SE530H35C3
Manufacturer Part Number
EP4SE530H35C3
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4SE530H35C3ES
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP4SE530H35C3N
Manufacturer:
ALTERA
Quantity:
586
Company:
Part Number:
EP4SE530H35C3NES
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4SE530H35C3NES
Manufacturer:
ALTERA
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 693 of 1154
- Download datasheet (32Mb)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
Transmitter Channel-to-Channel Skew Optimization for Modes Other than
Basic (PMA Direct) Mode
High-speed serial clock and low-speed parallel clock skew between channels and
unequal latency in the transmitter phase compensation FIFO contribute to transmitter
channel-to-channel skew. Transmitter datapath clocking is set up to provide low
channel-to-channel skew when compared with non-bonded channel configurations.
■
■
In bonded channel configurations—the high-speed serial clock and low-speed
parallel clock for all bonded channels are generated by the CMU0 clock divider or
the ATX clock divider block, resulting in lower channel-to-channel clock skew.
The transmitter phase compensation FIFO in all bonded channels (except in Basic
[PMA Direct] ×N mode) share common pointers and control logic generated in the
central control unit (CCU), resulting in equal latency in the transmitter phase
compensation FIFO of all bonded channels. The lower transceiver clock skew and
equal latency in the transmitter phase compensation FIFOs in all channels
provides lower channel-to-channel skew in bonded channel configurations.
In non-bonded channel configurations—the high-speed serial clock and low-speed
parallel clock in each channel are generated independently by its local clock
divider. This results in higher channel-to-channel clock skew.
The transmitter phase compensation FIFO in each non-bonded channel (except in
Basic [PMA Direct] mode) has its own pointers and control logic that can result in
unequal latency in the transmitter phase compensation FIFO of each channel. The
higher transceiver clock skew and unequal latency in the transmitter phase
compensation FIFO in each channel can result in higher channel-to-channel skew.
Stratix IV Device Handbook Volume 2: Transceivers
2–21
Related parts for EP4SE530H35C3
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: