EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Feature Summary PCI Express Compiler User Guide. February 2011 Altera Corporation ...

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... Figure 1–1 shows a high-level Stratix IV GX chip view. Figure 1–1. Stratix IV GX Chip View Note to Figure 1–1: (1) Resource counts vary with device selection, package selection, or both. February 2011 Altera Corporation chapter. (Note 1) General Purpose General Purpose PLL PLL I/O and Memory ...

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... General Purpose I/O and Memory Interface PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR PLL PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR PLL General Purpose I/O and Memory Interface February 2011 Altera Corporation ...

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... Figure 1–3 shows a high-level Stratix IV GT chip view. Figure 1–3. Stratix IV GT Chip View Note to Figure 1–3: (1) Resource counts vary with device selection, package selection, or both. February 2011 Altera Corporation chapter. (Note 1) General Purpose General Purpose PLL PLL I/O and Memory ...

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... Transaction layer support for up to two virtual channels (VCs) ■ Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Architecture Features PCI Express Compiler User Guide. February 2011 Altera Corporation ...

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... On-package and on-chip power supply decoupling to satisfy transient current ■ requirements at higher frequencies, thereby reducing the need for on-board decoupling capacitors ■ Calibration circuitry for transmitter and receiver on-chip termination (OCT) resistors February 2011 Altera Corporation PCI Express Compiler User Guide. Stratix IV Device Handbook Volume 1 1–7 ...

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... (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in Stratix IV GX and Stratix IV GT devices (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in ■ Stratix IV E devices Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Architecture Features February 2011 Altera Corporation ...

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... Programmable DQ group widths bits (includes parity bits) ■ Dynamic OCT, trace mismatch compensation, read-write leveling, and half-rate ■ register capabilities provide a robust external memory interface solution February 2011 Altera Corporation ) and on-chip parallel (R ) termination with auto-calibration for termination for differential I/Os D ratio of 8:1:1 to reduce loop inductance in the package— ...

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... I/O, power, and the JTAG pins to PCB, refer to the Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines Stratix IV GT Device Family Pin Connection Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Architecture Features and the Guidelines. February 2011 Altera Corporation ...

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Table 1–1 lists the Stratix IV GX device features. Table 1–1. Stratix IV GX Device Features (Part Feature EP4SGX70 EP4SGX110 EP4SGX180 Package Option ALMs 29,040 42,240 70,300 LEs 72,600 105,600 175,750 0.6 Gbps- 8.5 Gbps Transceivers — ...

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Table 1–1. Stratix IV GX Device Features (Part Feature EP4SGX70 EP4SGX110 EP4SGX180 Package Option M9K Blocks 462 660 (256 × 36 bits) M144K Blocks 16 16 (2048 × 72 bits) Total Memory (MLAB+M9K 7,370 9,564 13,627 +M144K) ...

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... Stratix IV devices accounts for the on-package F1517 F1760 F1932 (42.5 mm × 42.5 mm) (45 mm × 45 mm) (4), (6) (6) (6) — — — — — — KF40 — — KF40 — — KF40 KF43 NF45 KF40 KF43 NF45 KH40 (3) KF43 NF45 Package Information Datasheet for Altera Devices. ...

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... Altera Technical Support. ...

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... The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. (2) Four multiplier adder mode. (3) Total pairs of high-speed LVDS SERDES take the lowest channel count of R (4) This data is preliminary. February 2011 Altera Corporation EP4SE360 EP4SE530 780 1152 ...

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... The 1152-pin and 1517-pin for EP4SE530 and EP4SE820 devices are available only in the 42.5 mm × 42.5 mm Hybrid flip chip package. (4) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the Information Datasheet for Altera Devices. ...

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... The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. (5) This data is preliminary. February 2011 Altera Corporation EP4S40G5 EP4S100G2 ...

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... Devices under the same arrow sign have vertical migration capability. (3) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the Altera Device Package Information Data (4) EP4S40G5 and EP4S100G5 devices with 1517 pin-count are only available in 42.5-mm × 42.5-mm Hybrid flip chip packages. ...

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... Transceiver Count 180 D: 8 230 F: 16 290 H: 24 360 K: 36 530 N: 48 820 Package Type F: FineLine BGA (FBGA) H: Hybrid FineLine BGA February 2011 Altera Corporation Ball Array Dimension Corresponds to pin count 29 = 780 pins 35 = 1152 pins 40 = 1517 pins 43 = 1760 pins 45 = 1932 pins 1–19 ™ ...

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... Changes Table 1–7 and Table 1–8. Document Revision History Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices Speed Grade with 1 being the fastest Operating Temperature C: Commercial temperature ( Industrial temperature (t = 0°C to 100°C) J February 2011 Altera Corporation ...

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... Updated Table 1–2. ■ Updated “Table 1–5 shows the total number of transceivers available in the Stratix IV GT ■ Device.” on page 1–15. July 2008 1.1 Revised “Introduction”. May 2008 1.0 Initial release. February 2011 Altera Corporation Changes Stratix IV Device Handbook Volume 1 1–21 ...

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... Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Document Revision History February 2011 Altera Corporation ...