EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 9

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
February 2011 Altera Corporation
PLLs
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I/O Features
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High-Speed Differential I/O with DPA and Soft-CDR
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External Memory Interfaces
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Three to 12 PLLs per device supporting spread-spectrum input tracking,
programmable bandwidth, clock switchover, dynamic reconfiguration, and delay
compensation
On-chip PLL power supply regulators to minimize noise coupling
Sixteen to 24 modular I/O banks per device with 24 to 48 I/Os per bank designed
and packaged for optimal simultaneous switching noise (SSN) performance and
migration capability
Support for a wide range of industry I/O standards, including single-ended
(LVTTL/CMOS/PCI/PCIX), differential (LVDS/mini-LVDS/RSDS),
voltage-referenced single-ended and differential (SSTL/HSTL Class I/II) I/O
standards
On-chip series (R
single-ended I/Os and on-chip differential (R
Programmable output drive strength, slew rate control, bus hold, and weak
pull-up capability for single-ended I/Os
User I/O:GND:V
interface
Programmable transmitter differential output voltage (V
high-speed LVDS I/O
Dedicated circuitry on the left and right sides of the device to support differential
links at data rates from 150 Mbps to 1.6 Gbps
Up to 98 differential SERDES in Stratix IV GX devices, up to 132 differential
SERDES in Stratix IV E devices, and up to 47 differential SERDES in Stratix IV GT
devices
DPA circuitry at the receiver automatically compensates for channel-to-channel
and channel-to-clock skew in source synchronous interfaces
Soft-CDR circuitry at the receiver allows implementation of asynchronous serial
interfaces with embedded clocks at up to 1.6 Gbps data rate (SGMII and GbE)
Support for existing and emerging memory interface standards such as DDR
SDRAM, DDR2 SDRAM, DDR3 SDRAM, QDRII SRAM, QDRII+ SRAM, and
RLDRAM II
DDR3 up to 1,067 Mbps/533 MHz
Programmable DQ group widths of 4 to 36 bits (includes parity bits)
Dynamic OCT, trace mismatch compensation, read-write leveling, and half-rate
register capabilities provide a robust external memory interface solution
S
CC
) and on-chip parallel (R
ratio of 8:1:1 to reduce loop inductance in the package—PCB
T
) termination with auto-calibration for
D
) termination for differential I/Os
Stratix IV Device Handbook Volume 1
OD
) and pre-emphasis for
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