XA3S500E-4CPG132Q Xilinx Inc, XA3S500E-4CPG132Q Datasheet - Page 33

• Manufacturer Part Number: XA3S500E-4CPG132Q
• Description: IC FPGA SPARTAN-3E 500K 132CSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4CPG132Q

• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 92
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 132-TFBGA, CSPBGA
• Package: 132CSBGA
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 92
• Ram Bits: 368640
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface Configuration Timing
Table 40: Timing for SPI Configuration Mode
Table 41: Configuration Timing Requirements for Attached SPI Serial Flash
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
T
T
T
T
T
T
T
T
T
T
T
f
C
Symbol
CCLK1
CCLKn
MINIT
INITM
CCO
DCC
CCD
CCS
DSU
DH
V
Symbol
or f
These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
Subtract additional printed circuit board routing delay as required by the application.
R
R
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends
on specific read command used)
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] and M[2:0] mode pins before the rising
edge of INIT_B
Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of
INIT_B
MOSI output valid after CCLK edge
Setup time on DIN data input before CCLK edge
Hold time on DIN data input after CCLK edge
Description
Description
www.xilinx.com
T
T
T
Minimum
CCS
V
DSU
f
C
T
≤
50
0
≥
DH
T
Requirement
≤
≤
MCCLn
------------------------------ -
T
T
≤
T
CCLKn min
MCCL1
MCCL1
(see
(see
T
See
See
See
MCCH1
1
Maximum
–
Table
Table
Table 38
Table 38
Table 38
(
T
–
–
DCC
-
-
T
T
)
CCO
34)
34)
CCO
Units
Units
MHz
ns
ns
ns
ns
ns
ns
33