XC3S1200E-5FTG256C Xilinx Inc, XC3S1200E-5FTG256C Datasheet - Page 138
![IC FPGA SPARTAN3E 1200K 256FTBGA](/photos/6/71/67101/pk053-256_sml.jpg)
XC3S1200E-5FTG256C
Manufacturer Part Number
XC3S1200E-5FTG256C
Description
IC FPGA SPARTAN3E 1200K 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-5FTG256C
Number Of Logic Elements/cells
19512
Number Of Labs/clbs
2168
Total Ram Bits
516096
Number Of I /o
190
Number Of Gates
1200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Quantity:
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Part Number:
XC3S1200E-5FTG256C(XC3S1200E-4FTG256I)
Manufacturer:
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0
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DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 98: CLB (SLICEM) Timing
138
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
Propagation Times
T
Set/Reset Pulse Width
T
AS
AH
CKO
DICK
CKDI
CH
CL
TOG
ILO
RPW_CLB
The numbers in this table are based on the operating conditions set forth in
Symbol
When reading from the FFX (FFY) Flip-Flop,
the time from the active transition at the CLK
input to data appearing at the XQ (YQ) output
Time from the setup of data at the F or G input
to the active transition at the CLK input of the
CLB
Time from the setup of data at the BX or BY
input to the active transition at the CLK input of
the CLB
Time from the active transition at the CLK input
to the point where data is last held at the F or
G input
Time from the active transition at the CLK input
to the point where data is last held at the BX or
BY input
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
The time it takes for data to travel from the
CLB’s F (G) input to the X (Y) output
The minimum allowable pulse width, High or
Low, to the CLB’s SR input
Description
www.xilinx.com
Table
0.46
1.58
0.70
0.70
1.57
Min
0
0
0
-
-
77.
-5
Max
0.52
0.66
657
Speed Grade
-
-
-
-
-
-
-
0.52
1.81
0.80
0.80
1.80
Min
DS312-3 (v3.8) August 26, 2009
0
0
0
-
-
-4
Product Specification
Max
0.60
0.76
572
-
-
-
-
-
-
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
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