XC3S1200E-5FTG256C Xilinx Inc, XC3S1200E-5FTG256C Datasheet - Page 171

IC FPGA SPARTAN3E 1200K 256FTBGA

XC3S1200E-5FTG256C

Manufacturer Part Number
XC3S1200E-5FTG256C
Description
IC FPGA SPARTAN3E 1200K 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet

Specifications of XC3S1200E-5FTG256C

Number Of Logic Elements/cells
19512
Number Of Labs/clbs
2168
Total Ram Bits
516096
Number Of I /o
190
Number Of Gates
1200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S1200E-5FTG256C
Manufacturer:
ALTERA
Quantity:
1 024
Part Number:
XC3S1200E-5FTG256C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1200E-5FTG256C
Manufacturer:
XILINX
0
Part Number:
XC3S1200E-5FTG256C
Manufacturer:
XILINX
Quantity:
500
Part Number:
XC3S1200E-5FTG256C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC3S1200E-5FTG256C(XC3S1200E-4FTG256I)
Manufacturer:
XILINX
0
User I/Os by Bank
Table 132
distributed between the four I/O banks on the VQ100 pack-
age.
Table 132: User I/Os Per Bank for XC3S100E, XC3S250E, and XC3S500E in the VQ100 Package
Footprint Migration Differences
The production XC3S100E, XC3S250E, and XC3S500E
FPGAs have identical footprints in the VQ100 package.
Designs can migrate between the devices without further
consideration.
DS312-4 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
Package
Edge
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
indicates how the 66 available user-I/O pins are
R
I/O Bank
0
1
2
3
Maximum
I/O
15
15
19
17
66
I/O
16
5
6
0
5
www.xilinx.com
INPUT
0
0
0
1
1
All Possible I/O Pins by Type
DUAL
18
21
1
0
2
VREF
1
1
1
1
4
(1)
Pinout Descriptions
CLK
0
24
8
8
8
(2)
(1)
171

Related parts for XC3S1200E-5FTG256C