XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 188
XC4VFX12-10SFG363C
Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC4VFX12-10SFG363C
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Xilinx Inc
Quantity:
10 000
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Chapter 5: Configurable Logic Blocks (CLBs)
188
Distributed RAM and Memory (Available in SLICEM only)
The configuration options for the set and reset functionality of a register or a latch are as
follows:
•
•
•
•
•
•
•
Multiple left-hand LUTs in SLICEMs can be combined in various ways to store larger
amounts of data.
The function generators (LUTs) in SLICEM can be implemented as a 16 x 1-bit synchronous
RAM resource called a distributed RAM element. RAM elements are configurable within a
CLB to implement the following:
•
•
•
•
Distributed RAM modules are synchronous (write) resources. A synchronous read can be
implemented with a storage element in the same slice. The distributed RAM and the
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
Single-Port 16 x 4-bit RAM
Single-Port 32 x 2-bit RAM
Single-Port 64 x 1-bit RAM
Dual-Port 16 x 2-bit RAM
CLK
Figure 5-4: Register/Latch Configuration in a Slice
CE
SR
BY
BX
LUT F Output
www.xilinx.com
LUT G Output
D
CE
CK
D
CE
CK
SR REV
SR REV
FFY
FFX
FF
LATCH
FF
LATCH
Q
Q
UG070 (v2.6) December 1, 2008
Attribute
Attribute
ug070_5_04_071504
Reset Type
Virtex-4 FPGA User Guide
INIT1
INIT0
SRHIGH
SRLOW
INIT1
INIT0
SRHIGH
SRLOW
SYNC
ASYNC
YQ
XQ
R
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