XC4VFX12-10FFG668I Xilinx Inc, XC4VFX12-10FFG668I Datasheet - Page 189
XC4VFX12-10FFG668I
Manufacturer Part Number
XC4VFX12-10FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
storage element share the same clock input. For a write operation, the Write Enable (WE)
input, driven by the SR pin, must be set High.
Table 5-3
configuration.
Table 5-3: Distributed RAM Configuration
For single-port configurations, distributed RAM has a common address port for
synchronous writes and asynchronous reads.
For dual-port configurations, distributed RAM has one port for synchronous writes and
asynchronous reads and another port for asynchronous reads. The function generator
(LUT) has separated read address inputs and write address inputs.
In single-port mode, read and write addresses share the same address bus. In dual-port
mode, one function generator (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs (Read) connected to the second
read-only port address and the W inputs (Write) shared with the first read/write port
address.
Figure
configurations occupying one slice.
Notes:
1. S = single-port configuration; D = dual-port configuration
5-5,
shows the number of LUTs (two per slice) occupied by each distributed RAM
16 x 1D
16 x 1S
32 x 1S
64 x 1S
Figure
RAM
5-6, and
WCLK
A[3:0]
WE
Figure 5-5: Distributed RAM (RAM16x1S)
D
www.xilinx.com
Figure 5-7
4
(BY)
(SR)
4
RAM 16x1S
WE
CK
A[4:1]
WG[4:1]
WSG
WS
Number of LUTs
RAM
illustrate various example distributed RAM
DI
1
2
2
4
D
(optional)
D
Q
ug070_5_05_071504
Output
Registered
Output
CLB Overview
189
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