XCV812E-7FG900C Xilinx Inc, XCV812E-7FG900C Datasheet - Page 11

• Manufacturer Part Number: XCV812E-7FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-7FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Dedicated Routing
Some signal classes require dedicated routing resources to
maximize performance. In the Virtex-E architecture, dedi-
cated routing resources are provided for two signal classes.
•
Clock Routing
Clock Routing resources distribute clocks and other signals
with very high fanout throughout the device. Virtex-E
devices include two tiers of clock routing resources referred
to as global and local clock routing resources.
•
Global Clock Distribution
Virtex-E provides high-speed, low-skew clock distribution
through the global routing resources described above. A
typical clock distribution net is shown in
DS025-2 (v2.3) November 19, 2002
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in
The global routing resources are four dedicated global
nets with dedicated input pins that are designed to
distribute high-fanout clock signals with minimal skew.
Each global clock net can drive all CLB, IOB, and block
RAM clock pins. The global nets can be driven only by
global buffers. There are four global buffers, one for
each global net.
Figure 9: Global Clock Distribution Network
Global Clock Rows
R
GCLKBUF3
GCLKPAD3
GCLKBUF1
GCLKPAD1
CLB
Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes
Figure
GCLKBUF0
GCLKPAD2
GCLKBUF2
GCLKPAD0
8.
Figure
CLB
Global Clock Column
XCVE_009
9.
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
CLB
•
•
•
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
global nets that in turn drive any clock pin.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the gen-
eral purpose routing.
Digital Delay-Locked Loops
There are eight DLLs (Delay-Locked Loops) per device,
with four located at the top and four at the bottom,
Figure
between the clock input pad and the internal clock input pins
throughout the device. Each DLL can drive two global clock
networks.The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element.
Additional delay is introduced such that clock edges arrive
at internal flip-flops synchronized with clock edges arriving
at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB. Global Clock Distribution
Network.
DLL Location
The local clock routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These local resources are
more flexible than the global resources since they are
not restricted to routing only to clock pins.
10. The DLLs can be used to eliminate skew
CLB
buft_c.eps
Tri-State
Lines
Module 2 of 4
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