XCV812E-7FG900C Xilinx Inc, XCV812E-7FG900C Datasheet - Page 77
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XCV812E-7FG900C
Manufacturer Part Number
XCV812E-7FG900C
Description
IC FPGA 1.8V C-TEMP 900-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-E EMr
Datasheet
1.XCV405E-6FG676C.pdf
(118 pages)
Specifications of XCV812E-7FG900C
Number Of Logic Elements/cells
21168
Number Of Labs/clbs
4704
Total Ram Bits
1146880
Number Of I /o
556
Number Of Gates
254016
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
900-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCV812E-7FG900C
Manufacturer:
XILINX
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Company:
Part Number:
XCV812E-7FG900C
Manufacturer:
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DS025-4 (v1.6) July 17, 2002
Virtex-E Pin Definitions
DS025-4 (v1.6) July 17, 2002
GCK0, GCK1,
GCK2, GCK3
M0, M1, M2
CCLK
PROGRAM
DONE
INIT
BUSY/DOUT
D0/DIN,
D1, D2,
D3, D4,
D5, D6,
D7
WRITE
CS
TDI, TDO,
TMS, TCK
DXN, DXP
V
V
V
GND
CCINT
CCO
REF
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Pin Name
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Dedicated Pin
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
R
(Open-drain)
Bidirectional
Bidirectional
Direction
Input or
Input or
Output
Output
Output
Mixed
Input
Input
Input
Input
Input
Input
Input
Input
Input
N/A
0
0
Clock input pins that connect to Global Clock Buffers. These pins become
user inputs when not needed for clocks.
The configuration Clock I/O pin: it is an input for SelectMAP and slave-serial
modes, and output in master-serial mode. After configuration, it is input only,
logic level = Don’t Care.
sequence is in progress. The output can be open drain.
When Low, indicates that the configuration memory is being cleared. The pin
becomes a user I/O after configuration.
loaded. The pin becomes a user I/O after configuration unless the
SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data to
downstream devices in a daisy-chain. The pin becomes a user I/O after
configuration.
In SelectMAP mode, D0-7 are configuration data pins. These pins become
user I/Os after configuration unless the SelectMAP port is retained.
In bit-serial modes, DIN is the single data input. This pin becomes a user I/O
after configuration.
In SelectMAP mode, the active-low Write Enable signal. The pin becomes a
user I/O after configuration unless the SelectMAP port is retained.
user I/O after configuration unless the SelectMAP port is retained.
Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.
voltage is not needed (subject to banking rules).
Ground
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Mode pins are used to specify the configuration mode.
Initiates a configuration sequence when asserted Low.
Indicates that configuration loading is complete, and that the start-up
In SelectMAP mode, BUSY controls the rate at which configuration data is
In SelectMAP mode, the active-low Chip Select signal. The pin becomes a
Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
Power-supply pins for the internal core logic.
Power-supply pins for the output drivers (subject to banking rules)
Input threshold voltage pins. Become user I/Os when an external threshold
1-800-255-7778
0
Virtex™-E 1.8 V Extended Memory
Field Programmable Gate Arrays
Production Product Specification
Description
Module 4 of 4
1