XC4VFX100-10FFG1517I Xilinx Inc, XC4VFX100-10FFG1517I Datasheet - Page 162

• Manufacturer Part Number: XC4VFX100-10FFG1517I
• Description: IC FPGA VIRTEX-4FX 100K 1517FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX100-10FFG1517I

• Number Of Logic Elements/cells: 94896
• Number Of Labs/clbs: 10544
• Total Ram Bits: 6930432
• Number Of I /o: 768
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
162
Case 4: Reading From an Empty or Almost Empty FIFO
Prior to the operations performed in
this example, the timing diagram reflects standard mode. For FWFT mode, data at DO
appears one read-clock cycle earlier.
Clock Event 1: Read Operation and Assertion of ALMOSTEMPTY Signal
During a read operation to an almost empty FIFO, the ALMOSTEMPTY signal is asserted.
•
•
•
Clock Event 2: Read Operation and Assertion of EMPTY Signal
The EMPTY signal pin is asserted when the FIFO is empty.
•
•
•
In the event that the FIFO is empty and a write followed by a read is performed, the
EMPTY signal remains asserted.
Clock Event 3: Read Operation and Assertion of Read Error Signal
The read error signal pin is asserted when there is no data to be read because the FIFO is in
an EMPTY state.
•
AEMPTY
WRCLK
RDERR
EMPTY
RDCLK
WREN
RDEN
Figure 4-20: Reading From an Empty / Almost Empty FIFO (Standard Mode)
At time T
RDEN input of the FIFO.
At time T
outputs of the FIFO.
At time T
is asserted at the AEMPTY output pin of the FIFO.
Read enable remains asserted at the RDEN input of the FIFO.
At time T
the DO outputs of the FIFO.
At time T
output pin of the FIFO.
Read enable remains asserted at the RDEN input of the FIFO.
DO
FCKO_AEMPTY
FCCK_RDEN
FCKO_DO
FCKO_DO
FCKO_EMPTY
1
T
FCCK_RDEN
, after clock event 1 (RDCLK), data 00 becomes valid at the DO
, after clock event 2 (RDCLK), data 04 (last data) becomes valid at
00
T
FCKO_DO
, before clock event 1 (RDCLK), read enable becomes valid at the
, after clock event 2 (RDCLK), Empty is asserted at the EMPTY
www.xilinx.com
, one clock cycle after clock event 1 (RDCLK), ALMOSTEMPTY
01
T
FCKO_AEMPTY
Figure
T
FCKO_EMPTY
T
02
FCKO_DO
4-20, the FIFO is almost completely empty. In
T
FCKO_RDERR
03
2
UG070 (v2.6) December 1, 2008
04
3
Virtex-4 FPGA User Guide
T
FCKO_RDERR
4
ug070_4_20_071204
T
FCCK_RDEN
R