XC4VFX100-10FFG1517I Xilinx Inc, XC4VFX100-10FFG1517I Datasheet - Page 226

• Manufacturer Part Number: XC4VFX100-10FFG1517I
• Description: IC FPGA VIRTEX-4FX 100K 1517FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX100-10FFG1517I

• Number Of Logic Elements/cells: 94896
• Number Of Labs/clbs: 10544
• Total Ram Bits: 6930432
• Number Of I /o: 768
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
226
VHDL and Verilog Instantiation
VHDL and Verilog Templates
VHDL and Verilog instantiation templates are available for all primitives and submodules.
In VHDL, each template has a component declaration section and an architecture section.
Each part of the template should be inserted within the VHDL design file. The port map of
the architecture section should include the design signal names.
The ShiftRegister_C_x (with x = 16, 32, or 64) templates are cascadable modules and
instantiate the corresponding SRLCxE primitive (16) or submodule (32 or 64).
The ShiftRegister_16 template can be used to instantiate an SRL16 primitive.
In template nomenclature, the number indicates the number of bits (for example,
SHIFT_REGISTER_16 is the template for the 16-bit shift register). A “C” extension means
the template is cascadable.
The following are templates for primitives:
•
•
The following are templates for submodules:
•
•
The corresponding submodules have to be synthesized with the design.
Templates for the SHIFT_REGISTER_16_C module are provided in VHDL and Verilog
code as an example.
VHDL Template
SHIFT_REGISTER_16
SHIFT_REGISTER_C_16
SHIFT_REGISTER_C_32 (submodule: SRLC32E_SUBM)
SHIFT_REGISTER_C_64 (submodule: SRLC64E_SUBM)
-- Module: SHIFT_REGISTER_C_16
-- Description: VHDL instantiation template
-- CASCADABLE 16-bit shift register with enable (SRLC16E)
-- Device: Virtex-4 Family
---------------------------------------------------------------------
-- Components Declarations:
--
component SRLC16E
end component;
-- Architecture
--
-- Attributes for Shift Register initialization ("0" by default):
);
);
port (
INIT : bit_vector := X"0000"
CE
CLK
A0
A1
A2
A3
Q
Q15
D : in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic;
: out std_logic
Section:
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UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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