XCV812E-8FG900C Xilinx Inc, XCV812E-8FG900C Datasheet - Page 31

• Manufacturer Part Number: XCV812E-8FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-8FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Conflict Resolution
The block SelectRAM+ memory is a true dual-read/write
port RAM that allows simultaneous access of the same
memory cell from both ports. When one port writes to a
given memory cell, the other port must not address that
memory cell (for a write or a read) within the clock-to-clock
setup window. The following lists specifics of port and mem-
ory cell write conflict resolution.
•
•
Conflicts do not cause any physical damage.
Single Port Timing
Figure 33
SelectRAM+ memory. The block SelectRAM+ AC switching
characteristics are specified in the data sheet. The block
SelectRAM+ memory is initially disabled.
At the first rising edge of the CLK pin, the ADDR, DI, EN,
WE, and RST pins are sampled. The EN pin is High and the
WE pin is Low indicating a read operation. The DO bus con-
tains the contents of the memory location, 0x00, as indi-
cated by the ADDR bus.
At the second rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN and WE pins
are High indicating a write operation. The DO bus mirrors
the DI bus. The DI bus is written to the memory location
0x0F.
At the third rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is High
DS025-2 (v2.3) November 19, 2002
If both ports write to the same memory cell
simultaneously, violating the clock-to-clock setup
requirement, consider the data stored as invalid.
If one port attempts a read of the same memory cell
the
clock-to-clock setup requirement, the following occurs.
-
-
-
The write succeeds
The data out on the writing port accurately reflects
the data written.
The data out on the reading port is invalid.
other
shows a timing diagram for a single port of a block
R
simultaneously
writes,
violating
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
the
and the WE pin is Low indicating a read operation. The DO
bus contains the contents of the memory location 0x7E as
indicated by the ADDR bus.
At the fourth rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is Low
indicating that the block SelectRAM+ memory is now dis-
abled. The DO bus retains the last value.
Dual Port Timing
Figure 34
read/write block SelectRAM+ memory. The clock on port A
has a longer period than the clock on Port B. The timing
parameter T
diagram. The parameter, T
gram. All other timing parameters are identical to the single
port version shown in
T
are the same and at least one port is performing a write
operation. When the clock-to-clock set-up parameter is vio-
lated for a WRITE-WRITE condition, the contents of the
memory at that location are invalid. When the clock-to-clock
set-up parameter is violated for a WRITE-READ condition,
the contents of the memory are correct, but the read port
has invalid data. At the first rising edge of CLKA, memory
location 0x00 is to be written with the value 0xAAAA and is
mirrored on the DOA bus. The last operation of Port B was
a read to the same memory location 0x00. The DOB bus of
Port B does not change with the new value on Port A, and
retains the last read value. A short time later, Port B exe-
cutes another read to memory location 0x00, and the DOB
bus now reflects the new memory value written by Port A.
At the second rising edge of CLKA, memory location 0x7E
is written with the value 0x9999 and is mirrored on the DOA
bus. Port B then executes a read operation to the same
memory location without violating the T
the DOB reflects the new memory values written by Port A.
BCCS
is only of importance when the address of both ports
shows a timing diagram for a true dual-port
BCCS
, (clock-to-clock set-up) is shown on this
Figure
BCCS
33.
is violated once in the dia-
BCCS
parameter and
Module 2 of 4
27