XCV812E-8FG900C Xilinx Inc, XCV812E-8FG900C Datasheet - Page 32

• Manufacturer Part Number: XCV812E-8FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-8FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
At the third rising edge of CLKA, the T
violated with two writes to memory location 0x0F. The DOA
and DOB busses reflect the contents of the DIA and DIB
busses, but the stored value at 0x0F is invalid.
At the fourth rising edge of CLKA, a read operation is per-
formed at memory location 0x0F and invalid data is present
Module 2 of 4
28
Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory
ADDR_A
ADDR_B
CLK_A
CLK_B
WE_A
WE_B
DO_A
DO_B
EN_A
EN_B
Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory
DI_A
DI_B
ADDR
DOUT
RST
CLK
DIN
WE
EN
DISABLED
1111
00
MEM (00)
AAAA
00
T
BCCS
BCCS
T
T
T
T
BPWH
1111
BACK
BDCK
BECK
00
DDDD
AAAA
T
00
BCKO
READ
T
parameter is
BWCK
AAAA
MEM (00)
9999
VIOLATION
7E
1111
T
7E
BCCS
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1-800-255-7778
9999
9999
CCCC
0F
WRITE
BBBB
on the DOA bus. Port B also executes a read operation to
memory location 0x0F and also reads invalid data.
At the fifth rising edge of CLKA a read operation is per-
formed that does not violate the T
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
CCCC
AAAA
0F
0F
T
BPWL
BBBB
AAAA
1111
BBBB
0F
7E
UNKNOWN
READ
0000
MEM (7E)
0F
T
BCCS
UNKNOWN
2222
7E
ds022_0343_121399
DISABLED
2222
8F
2222
DS025-2 (v2.3) November 19, 2002
1111
7E
ds022_035_121399
FFFF
2222
1A
FFFF
BCCS
parameter to the
R