XC4010D-5PQ160C Xilinx Inc, XC4010D-5PQ160C Datasheet - Page 4

• Manufacturer Part Number: XC4010D-5PQ160C
• Description: IC LOGIC CL ARRAY 10K GAT 160PQ
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010D-5PQ160C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Number Of I /o: 129
• Number Of Gates: 10000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 160-BQFP
• Case: QFP160
• Dc: 96+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1072

G4
G3
G2
G1
F4
F3
F2
F1
XC4000, XC4000A, XC4000H Logic Cell Array Families
Figure 1. Simplified Block Diagram of XC4000-Families Configurable Logic Block
independently for each of the two registers; this input also
can be disabled for either flip-flop. A separate global Set/
Reset line (not shown in Figure 1) sets or clears each
register during power-up, reconfiguration, or when a dedi-
cated Reset net is driven active. This Reset net does not
compete with other routing resources; it can be connected
to any package pin as a global reset input.
Each flip-flop can be triggered on either the rising or falling
clock edge. The source of a flip-flop data input is program-
mable: it is driven either by the functions F', G', and H', or
the Direct In (DIN) block input . The flip-flops drive the XQ
and YQ CLB outputs.
In addition, each CLB F' and G' function generator con-
tains dedicated arithmetic logic for the fast generation of
carry and borrow signals, greatly increasing the efficiency
K
(CLOCK)
FUNCTION
FUNCTION
LOGIC
LOGIC
G1-G4
F1-F4
OF
OF
G'
F'
FUNCTION
LOGIC
F', G',
AND
OF
H1
H'
H1
C1
DIN
F'
G'
H'
G'
H'
H'
F'
DIN
F'
G'
H'
DIN
C2
2-10
C3
S/R
and performance of adders, subtracters, accumulators,
comparators and even counters.
Multiplexers in the CLB map the four control inputs, la-
beled C1 through C4 in Figure 1, into the four internal
control signals (H1, DIN, S/R, and EC) in any arbitrary
manner.
The flexibility and symmetry of the CLB architecture facili-
tates the placement and routing of a given application.
Since the function generators and flip-flops have inde-
pendent inputs and outputs, each can be treated as a
separate entity during placement to achieve high packing
density. Inputs, outputs, and the functions themselves can
freely swap positions within a CLB to avoid routing conges-
tion during the placement and routing operation.
C4
EC
MULTIPLEXER CONTROLLED
BY CONFIGURATUON PROGRAM
1
1
CONTROL
CONTROL
S/R
S/R
D
EC
D
EC
SD
RD
SD
RD
X6099
Q
Q
BYPASS
BYPASS
XQ
YQ
Y
X