XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 33

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

Longlines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances. In XC4000EX
devices, quad lines are preferred for critical nets, because
the buffered switch matrices make them faster for high fan-
out nets.
Two horizontal longlines per CLB can be driven by 3-state
or open-drain drivers (TBUFs). They can therefore imple-
ment unidirectional or bidirectional buses, wide multiplex-
ers, or wired-AND functions. (See
page 29
Each horizontal longline driven by TBUFs has either two
(XC4000E) or eight (XC4000EX) pull-up resistors. To acti-
vate these resistors, attach a PULLUP symbol to the long-
line net. The software automatically activates the appropri-
ate number of pull-ups. There is also a weak keeper at
each end of these two horizontal longlines. This circuit pre-
vents undefined floating levels. However, it is overridden by
any driver, even a pull-up resistor.
Each XC4000E longline has a programmable splitter switch
at its center, as does each XC4000EX longline driven by
TBUFs. This switch can separate the line into two indepen-
dent routing channels, each running half the width or height
of the array.
Each XC4000EX longline not driven by TBUFs has a buff-
ered programmable splitter switch at the 1/4, 1/2, and 3/4
points of the array. Due to the buffering, XC4000EX lon-
gline performance does not deteriorate with the larger array
sizes. If the longline is split, the resulting partial longlines
are independent.
Routing connectivity of the longlines is shown in
on page
September 18, 1996 (Version 1.04)
for more details.)
34.
“Three-State Buffers” on
Figure 27
Direct Interconnect (XC4000EX only)
The XC4000EX offers two direct, efficient and fast connec-
tions between adjacent CLBs. These nets facilitate a data
flow from the left to the right side of the device, or from the
top to the bottom, as shown in
the direct interconnect exhibit minimum interconnect prop-
agation delay and use no general routing resources.
The direct interconnect is also present between CLBs and
adjacent IOBs. Each IOB on the left and top device edges
has a direct path to the nearest CLB. Each CLB on the
right and bottom edges of the array has a direct path to the
nearest two IOBs, since there are two IOBs for each row or
column of CLBs.
The place and route software uses direct interconnect
whenever possible, to maximize routing resources and min-
imize interconnect delays.
Figure 31: XC4000EX Direct Interconnect
IOB
IOB
IOB
IOB
~ ~
CLB
CLB
~ ~
~ ~
CLB
CLB
Figure
~ ~
31. Signals routed on
~ ~
CLB
CLB
~ ~
IOB
IOB
IOB
IOB
X6603
4-37